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Intro Ctrl Sys Final Exam 2nd Semester 1920
Cơ sở y khoa (AS3105)
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R(s) Y(s) +_
Figure 1
C sG )( sG )(
Lecturer: (Date) Approved by: (Date)
(Signature & Fullname) (Signature, Position & Fullname)
UNIVERSITY OF TECHNOLOGY - VNUHCM FACULTY OF EEE
FINAL EXAM
Semester/Academic year 2 2019-
Date 24/7/ Course title Introduction to Control Systems Course ID 409401 Duration 90 mins. Question sheet code
Notes
:
- Students are allowed to use references, but not mobile phones and laptops
(The above part must be hidden when copying for exam)
Problem 1: (L.O) (2 points) Given a control system in Figure 1, in which:
- 6 ( ) ( 3)
s e G s s s
,
G sC ( ) 2
1 Calculate the steady state error to unit step input and unit ramp input.
1 Estimate the percentage of overshoot and settling time of the system using frequency response
Problem 2: (L.O.5) (3 points) Given a control system in Figure 1, in which
2
80( 1)
( )
( 4)
s G s s s
+
=
+
Design the phase lead controller GC ( s ) so that the closed-loop system has phase margin
- 0 F ³ M 65 and
steady-state error to unit ramp input
ess =0.
.
Problem 3: (L.O.5) (3 points) Given a control system in Figure 1, in which
10
( )
( 1)( 8)
G s s s
.
Design the PID controller
G sC ( ) such that the closed-loop system is expected to have POT 10%,
ts 1 (sec) (5% criterion) and steady state error to ramp input is 0.
Problem 4: (L.O.5) (2 points) Given a system described by the state equation:
0 1
2 1
A
é ù =ê ú ê- - ú ë û,
1
2
B
, [ ]
C =1 0
4 Verify the the system is controllable.
4 Design the state feedback controller so that poles of the closed loop system are - ± 4 j 4
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Intro Ctrl Sys Final Exam 2nd Semester 1920
Course: Cơ sở y khoa (AS3105)
