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ECE252 Exam 2 - Study guide for Exam 2.

Study guide for Exam 2.

Course

Introduction To Computer Engineering (COMP SCI/E C E 252)

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University of Wisconsin-Madison

Academic year: 2020/2021

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electronic switches --- switches controlled electronically instead of by mechanical action, the foundation upon which all modern computers are built

switch open --- light off, open/ broken circuit, powers voltage cannot push electrons through the bulb

switch closed --- on, complete circuit, powers voltage can push electrons through the bulb

transistors --- electronic switches made of semiconductor materials

MOS --- metal oxide semiconductor

voltage --- transistors use at their "gate" to open or close the switch

N-type --- +V at gate closes the switch, negative side electron switch, pulls out down to 0V

P-type --- 0V at gate closes the switch, positive side electron switch, pulls out up to +V

CMOS --- complementary MOS

CMOS logic gates --- N-type and P-type MOS transistors are used

Not Gate CMOS ---

not gate logic ---

NOR gate CMOS ---

OR gate CMOS --- NOR gate notted

serial connection (NOR) --- on top both inputs must be a 0 to pull c up to 1

parallel connection (NOR) --- on bottom only on input must be 1 to pull c down to 0

NOR gate logic ---

OR gate logic ---

NAND gate CMOS ---

AND gate CMOS ---

parallel connection (NAND) --- on top only one input must be 0 to pull c up to 1

serial connection (NAND) --- on bottom both inputs must be 1 to pull c down to 0

NAND gate logic ---

AND gate logic ---

implementing a truth table with AND, OR, and NOT gates --- 1. for each row with 1 as its result AND the input combination using NOT for the inputs that are 0 2. OR the outputs of AND gates

DeMorgan's Law --- NOT(NOT A AND NOT B) = A or B

combinational logic circuits --- produce output that depend only on the input

four-bit adder --- each component represents the full-adder logic implemented. connect the components to make an adder for 4-bit inputs

decoder --- sets to 1 one of its 2^n outputs given n input bits

multiplexer --- selects for its outputs one of its 2^n inputs given n selector bits

sequential logic circuits --- produce outputs that depends on their inputs and their state

M[address] --- means contents (i. data) in the memory location at address

ROM --- Read Only Memory, retains data when powered off

RAM --- Random Access Memory, can read and write but loses data when powered off

SRAM --- static RAM, faster but smaller in capacity than DRAM

DRAM --- Dynamic RAM, slower but much larger in capacity than SRAM however the data must be refreshed

flash --- very slow and very large, like RAM where you can read and write but also like ROM where it retains data

Memory cell circuit --- stores 1 bit inputs: S select determines if a cell is active WE write enable D(in) data in D(out) data out

memory array circuit --- the address decoder selects which memory location is active the output MUX passes out the active memory location for reading

finite state machines --- used to design machines that sequence through states is another mathematic model of computation combines combinational and sequential logic has a limited number of states is equivalent to a regular expression engine

sate of as ysem --- is a snapshot of all the relevant elements of the system at the moment the snapshot is taken

state diagram --- circles correspond to states arrows correspond to inputs, which might cause a state transition

output can be associated with the states or with arrows and for some just don't include

FSM --- computes the next states and outputs from current state and inputs

a finite number of states - SL(Sequential logic) stores states
a finite number of inputs - might cause state transitions
a finite number of outputs - results from state transitions
a specification of all state transitions - CL implements this
a specification of what causes each output value - CL implements this

clock --- typically used to insure FMS transitions are don synchronously (at the same time)

hertz --- number of cycles per second (unit of frequency)

overclocking --- running the clock at a higher frequency than what's specified to increase performance

flip flop --- fundamental building blocks f computers

gated D-latch --- commonly called a D flip flop when cnnected to a clock

flip flops in FSMs --- to isolate the current stated (denoted as Qt or S) from the next state (denoted as Qt+1 or S') that the FMS's C; computes

master-slave flip flop --- add a clock signal to make the flip flops function alternately

when clock is 0 --- slave flip flop is active so current state changes since its written into SFF master flip flop is inactive as CL computes the next state

when clock is 1 --- master flip flip is active so next state that was computed by CL is written into MFF slave flip flop is inactive so current state doesn't change

number of flip flops --- determined by the number of state bits

LC-3 has 16 bits transmits all bits in a word simultaneously , it's a parallel bus with a wire connection for each bit position

word --- the size in bits of info transmitted and processed internally in a processor

input/output --- are devises for getting data into and out of a computer each device has its own interface that typically use register

device driver --- a program that controls an I/O device

load --- is an instruction that reads the memory location at a specified address

store --- is an instruction that writes the memory location at a specific address

instructions --- the fundamental unit of work done by a processor specifies opcode and operands

opcode --- operation to be performed

operands --- data/locations to be used by operation

CISC --- complec Instruction Set Computer, have varibale-length instructions

RISC --- Reduced Instruction Set Computers, have fixed-length instructions

fetch instruction --- loads the next instruction to IR 1a. MAR <- PC CU copies contents of PC into MAR b. PC <- PC+1 CU increments PC to address of new next instruction 2. MDR <- M[MAR] CU sends a :read" signal causing the memory arry to copy data into MDR 3. IR <- MDR CU copies contents of MDR into IR

decode instruction --- decomposes the instruction into the IR into its parts

identify the OP code
identify the operand, if any

evaluate address --- calculates an address, if needed effective address - an address that's calculated addressing mode - specifies how to calculate the effective address

fetch operand --- get source opernads if any

execute operation --- does the operation, if needed

store results --- writes result to destination operand, if needed

sequencing exection flow --- doing one step after another

selecting exection flow --- controlling what steps to do next

repeating exection flow --- controlling whether to do the same steps again

programming paradigms --- imperative - state exactly how execution flow changes a computer's state to achieve desired result declarative - declare what result is desired with out saying how to achieve it

machine instructions --- control instructions - jump and branch computational instructions - ADD, AND,... data movement instructions - load, store

jump --- an unconditional instruction always changes PC to target address

branch --- a conditional instruction changes PC to target address, only if some condition is true

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