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Lecture 22
Microprocessors and Peripheral Devices (EEN-204)
Indian Institute of Technology Roorkee
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Lecture-22:
9. LHLD ADDR : This is an ALP statement. LHLD is the mnemonic for LOAD (H,L) REGISTER PAIR DIRECT. The meaning of the instruction is <Load the content of the memory location whose address is directly available as 2nd & 3rd byte of the instruction to register L and the content of the memory location at next higher address to the register H=. This is a 3-byte instruction. The instruction format is
0 0 1 0 1 0 1 0 N <B 2 > N+ <B 3 > N+
The macro RTL implemented is (L) M(B 3 , B 2 ) (H) M((B 3 , B 2 ) + 1) This instruction has no variation. The addressing mode is direct addressing mode. The micro RTL flow is: Machine Cycle- 1: OFMC : Status signals IO/M =0, S 1 =1, S 0 = T 1 : A 15 -A 8 (PCH), AD 7 -AD 0 (PCL), ALE = T 2 : RD = 0, (PC) (PC) +1, AD 7 -AD 0 M(AB)
T 3 : RD = 1, , (IR) AD 7 -AD 0 T 4 : 𝔇𝕝 decodes the opcode. LHLD addr = 1.
Machine Cycle- 2: MRMC : Status signals IO/M =0, S 1 =1, S 0 = T 1 : A 15 -A 8 (PCH), AD 7 -AD 0 (PCL), ALE = T 2 : RD = 0, (PC) (PC) +1, AD 7 -AD 0 M(AB)
T 3 : RD = 1, , (Z) AD 7 -AD 0
Machine Cycle- 3:
MRMC : Status signals IO/M =0, S 1 =1, S 0 = T 1 : A 15 -A 8 (PCH), AD 7 -AD 0 (PCL), ALE =
T 2 : RD = 0, (PC) (PC) +1, AD 7 -AD 0 M(AB) T 3 : RD = 1, , (W) AD 7 -AD 0
Machine Cycle- 4: MRMC : Status signals IO/M =0, S 1 =1, S 0 = T 1 : A 15 -A 8 (W), AD 7 -AD 0 (Z), ALE =
T 2 : RD = 0, AD 7 -AD 0 M(AB)
T 3 : RD = 1, , (L) AD 7 -AD 0
Machine Cycle- 5: MRMC : Status signals IO/M =0, S 1 =1, S 0 = T 1 : A 15 -A 8 (W), AD 7 -AD 0 (Z+1), ALE = T 2 : RD = 0, AD 7 -AD 0 M(AB)
T 3 : RD = 1, , (H) AD 7 -AD 0 The instruction requires 5 machine cycles- OFMC & fours MRMC and total number of 16 states. It needs 8μsec using 2 MHz internal
This instruction has no variation. The addressing mode is direct addressing mode. The data flow during the execution of instruction is shown in fig.5.
Fig.5 Data Flow during the Execution of SHLD Addr Instruction The micro RTL flow is: Machine Cycle- 1: OFMC : Status signals IO/M =0, S 1 =1, S 0 = T 1 : A 15 -A 8 (PCH), AD 7 -AD 0 (PCL), ALE = T 2 : RD = 0, (PC) (PC) +1, AD 7 -AD 0 M(AB)
T 3 : RD = 1, , (IR) AD 7 -AD 0 T 4 : 𝔇𝕝 decodes the opcode. SHLD addr = 1.
Machine Cycle- 2: MRMC : Status signals IO/M =0, S 1 =1, S 0 = T 1 : A 15 -A 8 (PCH), AD 7 -AD 0 (PCL), ALE = T 2 : RD = 0, (PC) (PC) +1, AD 7 -AD 0 M(AB)
T 3 : RD = 1, , (Z) AD 7 -AD 0
W Z
Y 3 Y 2 Y 1 Y 0 Z 1 Z 0
IR
22 H
X 3 X 2 X 1 X 0 PC
X 3 X 2 X 1 X 0 N
BDB
16 AB
8
Memory Y 1 Y 0 N+ N+
Z 1 Z 0
Y 3 Y 2 Y 3 Y 2 Y 1 Y 0
Z 3 Z 2
Z 3 Z 2 H L
Machine Cycle- 3:
MRMC : Status signals IO/M =0, S 1 =1, S 0 = T 1 : A 15 -A 8 (PCH), AD 7 -AD 0 (PCL), ALE = T 2 : RD = 0, (PC) (PC) +1, AD 7 -AD 0 M(AB)
T 3 : RD = 1, , (W) AD 7 -AD 0
Machine Cycle- 4: MWRMC : Status signals IO/M =0, S 1 =0, S 0 = T 1 : A 15 -A 8 (W), AD 7 -AD 0 (Z), ALE =
T 2 : WR = 0, AD 7 -AD 0 (L) T 3 : WR = 1, , M(AB) AD 7 -AD 0
Machine Cycle- 5: MWRMC : Status signals IO/M =0, S 1 =0, S 0 = T 1 : A 15 -A 8 (W), AD 7 -AD 0 (Z+1), ALE = T 2 : WR = 0, AD 7 -AD 0 (H)
T 3 : WR = 1, , M(AB) AD 7 -AD 0 The instruction requires 5 machine cycles- OFMC, two MRMC & two MWRMC and total number of 16 states. It needs 8μsec using 2 MHz internal clock.
11. LDAX rp : This is an ALP statement. LDAX is the mnemonic for LOAD ACCUMULATOR INDIRECTLY. As discussed earlier, the alphabet >X? in the mnemonic tells that a register pair is involved in the instruction. >rp? stands for register pair. The meaning of the
12. STAX rp: This is an ALP statement. STAX is the mnemonic for store accumulator indirectly using register indirect addressing mode. The meaning of the instruction is <Store the content of accumulator in the memory location whose address is available in register pair specified in the instruction=. The macro RTL implemented is M(rpH, rpL) (A) This is a single byte instruction. The instruction format is
0 0 R P 0 0 1 0 N
This instruction also has only two variations. RP = 00 and 01 are allowed for register pair (B, C) and (D, E) respectively. The micro RTL flow is Machine Cycle- 1:
OFMC : Status signals IO/M =0, S 1 =1, S 0 = T 1 : A 15 -A 8 (PCH), AD 7 -AD 0 (PCL), ALE = T 2 : RD = 0, (PC) (PC) +1, AD 7 -AD 0 M(AB)
T 3 : RD = 1, , (IR) AD 7 -AD 0 T 4 : 𝔇𝕝 decodes the opcode. LDAX rp = 1.
Machine Cycle- 2:
MWRMC : Status signals IO/M =0, S 1 =0, S 0 = T 1 : A 15 -A 8 (rpH), AD 7 -AD 0 (rpL), ALE = T 2 : WR = 0, AD 7 -AD 0 (A)
T 3 : WR = 1, , M(AB) AD 7 -AD 0
This instruction requires 2 machine cycles OFMC & MWRMC and 7 states. It needs 3 μsec using 2MHz clock. The addressing mode is register indirect addressing mode.
Lecture 22
Course: Microprocessors and Peripheral Devices (EEN-204)
University: Indian Institute of Technology Roorkee
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